Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
More recently, architectures for beamforming in multiple-input multiple-output (“MIMO”) wireless communication systems have used a feedback channel from the receiver to the transmitter. Wireless communication systems involved in beamforming can also be MISO (multiple-input single-output) systems. The feedback channel is used to communicate information regarding the spatial channel, or simply “channel”, (i.e. channel state information (“CSI”)), in order to tailor communication from the transmitter to the receiver. This feedback channel may use a wireless channel. The CSI estimated at the receiver is conventionally quantized (e.g., represented using a finite number of bits) before being sent to the transmitter. As is known, the IEEE 802.16 standard used 6 bits to represent a spatial channel from one transmitter to one receiver (e.g., 6 bits to represent a complex number). As an example, for a MISO channel with 4 transmit antennas and 1 receive antenna, an implementation for this would use 24 bits.
As is known, a receiver transmits feedback information, and this feedback information is conventionally associated with inner-symbol interference (“ISI”), fading, among other types of information associated with reflection-induced hindrances to communication between transmitter and receiver. For MIMO and MISO wireless communication systems, multiple antennas may be used at both receiver and transmitter or only at the transmitter. Accordingly, the number of possible spatial channels which may be used increases with the number of antennas used. Thus, the need for feedback channel bandwidth likewise increases with an increase in the number of spatial communication channels as previously described. To combat the increased demand for feedback channel bandwidth associated with MISO and MIMO beamforming applications, the IEEE 802.16e standard has included a low bit-rate feedback scheme. However, such a low bit-rate feedback scheme is significantly computationally intensive and thus may involve implementing a significant number of hardware resources, including a significant number of multipliers.
An Orthogonal Frequency Division Multiplexing (“OFDM”) wireless communication system may divide a broad band wireless channel into a set of parallel narrow band channels. These narrow band channels in the context of OFDM wireless communication system may be referred to as sub-channels or subcarriers. Multiple antennas at the transmitter or receiver can be added to an OFDM system to form MIMO-OFDM or MISO-OFDM systems. Such a MIMO-OFDM or MISO-OFDM system can be considered to add MIMO or MISO capability to each of the parallel narrowband channels. The above mentioned low bit rate feedback scheme refers to feeding back CSI for one or more of parallel narrow band channels, also referred to earlier as sub-channels or subcarriers.
Accordingly, it would be both desirable and useful to provide means for generally minimizing the computational/hardware complexity associated with implementing the low bit-rate feedback from a receiver to a transmitter. Furthermore, it would be both desirable and useful if such means for low bit-rate feedback approximated performance of the more computationally intensive IEEE 802.16e low bit-rate feedback scheme and could be used in systems using the low bit-rate feedback IEEE 802.16e scheme.